Fpga Prototyping of a Scan Based Design in an Ieee 1500 Wrapped Core

Verifying and validating complex IC designs on an FPGA prototype prior to device fabrication can provide many advantages. However, there is a lack of proper Electronic Design Automation (EDA) tool support to integrate and verify scan-based Design-for-Testability (DFT) circuitry on an FPGA. Integrating DFT technology on an FPGA prior to IC fabrication is complicated by process incompatibilities and conversion techniques are sub-optimal. This paper presents a simple design flow modification that automates the design of scan-based DFT structures on an FPGA device. The proposed design flow re-maps the scan chains, which is automatically generated by an ASIC design tool, into an FPGA design flow. To illustrate the proposed design flow, the wrapper cell design for system-on-chip (SOC) testing used in the IEEE 1500 standard is described in this paper 1 . We have shown that an SOC design with scan DFT architectures, which is initially targeted as an ASIC, can be easily re-targeted at FPGA devices for prototype development and validation. Our results show that the FPGA logic resources increase to accommodate the design flow, however the desired advantages of DFT prototype development are realized.